This is a 4 channel 10 bit and 1 channel 12 bit Successive Approximation ADC instantiated in 0.18µM CMOS standard logic process. A power down mode is included with less than 1µA om standby current. All biasing circuits are included inquiring only an external voltage to define the full scale range.
This voltage is connected to the analog supply voltage.
> Process 0.18µM CMOS technology
> Standard Process: 1P5M 1.8/3.3V
> Resolution 12 bit
> Sampling Rate 500KHz maximum at 12 bit